This software solves the problem of Topoplogical Routing in VLSI designing. Given the circuit and terminal details, this software tells whether the terminals can be connected in a single layer as required and if yes, it shows how.
Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
VCD is a open format described in the Verilog HDL LRM. This format is widely used by VLSI engineers to exchange design description & data. The aim of the s/w here is to build a library of routines to parse and edit this format.
ASSL (pronounced AY-sil), is a wrapper around CHP, an established async. process description language. This project provides a set of tools that aid the design, simulation, and synthesis of async. VLSI circuits. Common parser, independent tool projects.