• Topological Routing (Home)
This software solves the problem of Topoplogical Routing in VLSI designing. Given the circuit and terminal details, this software tells whether the terminals can be connected in a single layer as required and if yes, it shows how.

"Magic" VLSI layout tool and various incarnations of the Berkeley tools.

Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.

VLSI Vision CPiA kernel driver & mediakit addon (for BeOS 4.5).

DICaD is a free EDA software for VLSI cirquits design.

VLSI is a flexible software framework for the easy implementation and evaluation of VLSI routing algorithms and the visualization of routing results.

  • VCD reader & editor (Home)
VCD is a open format described in the Verilog HDL LRM. This format is widely used by VLSI engineers to exchange design description & data. The aim of the s/w here is to build a library of routines to parse and edit this format.
  • Python EDA Initiative (Home)
Python EDA Initiative -- A suite of VLSI CAD tools for electronic design automation.
  • Async. Simulation and Synthesis Language (Home)
ASSL (pronounced AY-sil), is a wrapper around CHP, an established async. process description language. This project provides a set of tools that aid the design, simulation, and synthesis of async. VLSI circuits. Common parser, independent tool projects.